1. Field of the Invention
The present invention relates to the control of a photosensitive cell of an image sensor for use in shooting devices such as, for example, video cameras or digital photographic devices. More specifically, the present invention relates to a semiconductor monolithic photosensitive cell.
2. Discussion of the Related Art
FIG. 1 schematically illustrates the circuit of a photosensitive cell of an array of photosensitive cells distributed in rows and columns of an image sensor. To each photosensitive cell of the array are associated a reset device and a read device. The reset device is formed of an N-channel MOS transistor M1, interposed between a supply rail Vdd and a read node S. The gate of reset transistor M1 is capable of receiving a reset control signal RST. Read node S is capable of storing charges. For this purpose, a diode formed by a separate component may be connected to node S. The capacitance of node S may also correspond to the capacitances of the sources of transistors M1 and M4, to the input capacitance of transistor M2, and to all the stray capacitances present at node S.
The read device is formed of the series connection of first and second N-channel MOS transistors M2, M3. The drain of the first read transistor M2 is connected to supply rail Vdd. The source of the second read transistor M3 is connected to an output terminal P. The gate of first read transistor M2 is connected to read node S. The gate of second read transistor M3 is capable of receiving a read signal RD. The relative position of read transistors M2 and M3 may be inverted without substantially modifying the device operation.
The photosensitive cell comprises a photodiode D having its anode connected to a reference supply rail or circuit ground GND and its cathode connected to read node S via an N-channel MOS transfer transistor M4. The gate of transfer transistor M4 is capable of receiving a transfer control signal TX. Generally, signals RD, RST, and TX are provided by control circuits, not shown in FIG. 1, and may be simultaneously provided to all the photosensitive cells of the same row of the cell array. Output terminals P of the photosensitive cells of the same column are connected to a processing circuit (not shown).
FIG. 2 shows an example of a timing diagram of signals RD, RST, TX, of voltage VS between read node S and the circuit ground, and of voltage VD across photodiode D of the circuit of FIG. 1 between two read cycles of the photosensitive cell. Signals RD, RST, and TX are binary signals varying between high and low levels that can be different for each of the signals.
Duration TRD corresponds to the duration of a read cycle. At the beginning of a read cycle, a given amount of charges (electrons) is stored at the level of photodiode D. The read cycle starts when signal RD switches high, which corresponds to the selection of the array row containing the photosensitive cell to be read. Signal RST is then high. Reset transistor M1 is thus on. Voltage VS is then substantially equal to voltage Vdd. Signal RST is then set to the low state. Reset transistor M1 is then off. Voltage VS at read node S is then set to a reset level VRST that can be lower than voltage Vdd due to a coupling with reset transistor M1. Reset level VRST is generally disturbed by noise essentially coming from the thermal noise of the channel of reset transistor M1. This noise is sampled and maintained on the read node upon blocking of reset transistor M1. Reset level VRST is then stored outside the photosensitive cell via read transistors M2, M3.
Control signal TX is then set to the high state. Transfer transistor M4 is thus on, which enables transfer of the charges stored in photodiode D to read node S. Photodiode D is designed so that all the charges stored therein are transferred to read node S. Voltage VS then decreases to a useful signal level VU. Signal TX is then set back to the low level. Photodiode D is thus isolated again and, due to the lighting, charges are stored again. Useful signal level VU at read node S is then read via read transistors M2, M3. Like reset level VRST, useful signal level VU is disturbed, in particular, by the thermal noise of the channel of reset transistor M1 which has been sampled and maintained on the read node. The subtraction of signals VU and VRST by the processing circuit enables suppressing the noise of reset transistor M1 by a double correlated sampling. Signal RST is then set to the high level. Voltage VS at read node S is then maintained equal to voltage Vdd. The read cycle ends when signal RD is set to the low state to deselect the photosensitive cell.
Duration TFR between the beginning of two read cycles of the same row of photosensitive cells corresponds to the duration or period of an image sensor frame. Duration TIRD between the end of a read cycle of a cell row and the beginning of the next read cycle of the same cell row may be such that under too strong a lighting, a saturation of the photodiode may occur. It is thus preferable to limit duration TINT of the integration phase during which charges are formed and stored at the level of each photodiode D.
For this purpose, an example of a conventional control consists of maintaining reset control signal RST high for the entire duration TIRD between two read cycles of the same row. Transfer control signal TX is set to the high level little after the end of a read cycle. Photodiode D then permanently discharges towards the supply rail. Signal TX is set to the low state at the end of a duration TRST after the end of the read cycle, to start an integration phase.
For technologies of increasing density with photosensitive cells of small dimensions and control signals that become smaller and smaller, it becomes difficult to ensure proper transfer of charges from photodiode D to read node S during a read cycle or before the beginning of an integration phase.
To improve the charge transfer, the high level of signal TX applied on the gate of transfer transistor M4 is increased to increase the intensity of the electric field enabling flowing of the charges. However, if this level becomes too high, a potential well is created in the channel of transfer transistor M4 of a value greater than reset voltage VRST. Charges can then be stored during the charge transfer to the channel region of transfer transistor M4. Part of these charges can then be sent back to photodiode D at the falling edge of signal TX from the high level to the low level.
When the photosensitive cell is submitted to a low lighting, the charge return risk appears to be stronger with such an implementation when transfer signal TX is set to the low state before the beginning of an integration phase than during a read cycle. This may translate as a charge injection from read node S to the photodiode before the integration phase and may result in an offset of the signal subsequently measured in the absence of light, with an increase of non-uniformities at a low signal level.